Sequential decoder

ABSTRACT

A sequential decoder for decoding a systematic and convolutional code signal having a code rate greater than 1/2 and carrying out error correction coding of the code signal. A local most likely path in a plurality of possible paths for a newly received information bit is determined by calculating a branch metric indicating likelihood of each of the plurality of possible paths in accordance with a predetermined algorithm. The path decision is carried out by a construction including a two-path comparing path decision circuit which receives a pair of bits comprised of an information bit and a parity bit at one time and determining a local most likely path between two possible paths for the information bit. A four-path comparing path decision circuit receives a pair of information bits at one time and determines a local most likely path among four possible paths for the pair of information bits. A parity bit timing detecting circuit detects a timing of an input of the above pair of bits comprised of an information bit and a parity bit. A selecting circuit selects an output of the above two-path comparing path decision circuit at the input timing of the above pair of bits comprised of an information bit and a parity bit, and selects an output of the above four-path comparing path decision circuit at the timing of the input of the above pair of information bits.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a sequential decoder for decoding asystematic and convolutional code signal having a code rate greater than1/2 and carrying out error correction coding of the code signal. This isachieved by determining a local most likely path in a plurality ofpossible paths for a newly received information bit by calculating abranch metric indicating likelihood of each of the plurality of possiblepaths in accordance with a predetermined algorithm.

Error correction coding is used at a receiver side for enablingcorrection of errors occurring during transmission of data. FIG. 1 showsthe construction of an example of an encoder which receives a series ofbinary data consisting of information bits and generates a parity bitfor each information bit. That is, the encoder of FIG. 1 generates asystematic and convolutional code signal having a code rate of 1/2. Anexample of coded output corresponding to an input data series "0011101"is shown in FIG. 2.

Usually, sequential decoders have an internal encoder identical to theencoder by which the transmitted signal has been encoded on the senderside. The sequential decoders sequentially decode the transmitted signalusing an output of the internal encoder, and selects a local most likelyvalue, of the transmitted signal in a trial and error method. Theinternal encoder generates a parity bit from information bits which aredecoded in the sequential decoder.

Generally, a series of binary data can be expressed as a path consistingof a series of branches in a tree diagram as shown in FIG. 3. Therefore,the process of decoding encoded and transmitted data consists ofdetermining a local most likely path consisting of a series of branchesin a tree diagram, and locally (at each node of the tree diagram), theprocess of sequential decoding corresponds to determination (selection)of a local most likely branch in a plurality of branches extendingforward (to the right in FIG. 3) from the node.

Calculation of the likelihood for each branch, and the determination ofthe local most likely path is carried out in accordance with apredetermined algorithm. The most popular algorithm is known as the Fanoalgorithm, which is disclosed by R. M. Fano. in "Heuristic Discussion ofProbabilistic Decoding", IEEE Transaction of Information Theory, Vol.IT.19, April 1963, pp.64-73, and U.S. Pat. No. 3,457,562. As an otheralgorithm, the stack algorithm which was independently proposed by Z.Zigangirov ("Some Sequential Decoding Procedures", Probabl. PeredachiInf., Vol.2, No.4, 1966, pp.13-25), and F. Jelinek ("A Fast SequentialDecoding Algorithm Using a Stack", IBM J. Res. Dev., Vol.13, November1969, pp. 675-685), respectively, is known. The present invention isapplicable to a sequential decoder using both these algorithms.

In particular, error correction coding is used in the field of satellitecommunication because transmission length without a repeater is long andthe power of the received signal is small in satellite communication.

(2) Description of the Related Art

FIG. 4 is a block diagram of a conventional sequential decoder receivinga pair of signal bits consisting of an information bit and a parity bitat one time and sequentially decoding each signal bit using the Fanoalgorithm.

In the field of satellite communication, quadrature phase shift keyingis often used to modulate a signal to be transmitted. In the quadraturephase shift keying (QPSK), a pair of binary signals synchronized witheach other are modulated as four phase states of the carrier wave, i.e., the pair of baseband signals (1,1) is modulated to the phase stateπ/4, the pair of baseband signals (0,1) is modulated to the phase state3π/4, the pair of baseband signals (0,0) is modulated to the phase state-3π/4, and the pair of baseband signals (1,0) is modulated to the phasestate π/4. On the receiver side, received signals are first demodulatedto one of the above four pairs of baseband signals (1,1), (0,1), (0,0),and (1,0), and then are decoded in a sequential decoder.

When the transmitted signals are generated by the encoder as shown inFIG. 1, which generates a pair of coded signal bits consisting of aninformation bit and a parity bit as shown in FIG. 5, the above pair ofthe baseband signals may be the pair of output signals of the encoder.Therefore, the pair of input signals of the sequential decoder of FIG. 4may be the QPSK output of the above demodulator.

In FIG. 4, reference numeral 1 denotes a buffer memory, 2 denotes apointer, 4 denotes a path decision circuit, 5 denotes a search directioncontrol circuit, 6 denotes a path memory, and 7 denotes an addresscounter.

The buffer memory 1 receives and stores received and demodulated (coded)data consisting of a pair of bits comprised of an information bit and aparity bit.

The path decision circuit 4 receives a pair of coded signals consistingof an information bit and a parity bit at one time from the buffermemory 1, internally generates a parity bit from decoded informationbits by an internal encoder (not shown in FIG. 4) which is contained inthe path decision circuit 4, calculates the branch metric, which isdefined by Fano in the aforementioned publications, "HeuristicDiscussion of Probabilistic Decoding", IEEE Transaction on InformationTheory, Vol. IT-19, April 1963, pp.64-73, and the U.S. Pat. No.3,457,562, for each information bit, which indicates a local likelihoodfor each possible branch for the information bit in the forwarddirection from each node corresponding to the information bit in thetree diagram as shown in FIG. 3. The path decision circuit also selectsa local (at the node) most likely branch (path) based on theabove-calculated branch metric, and outputs the decoded signal bitscorresponding to the above-selected branch. The decoded signals are thenwritten in the path memory 6.

The above branch metric obtained in the path decision circuit 4 issupplied to the search direction control circuit 5.

The search direction control circuit 5 accumulates branch metrics of thebranches, each of which has been selected as a local most likely branchat each corresponding node on the selected path, to obtain the pathmetric, and holds the path metric. That is, the search direction controlcircuit 5 adds a branch metric in the forward direction which is newlyreceived from the path decision circuit 4, to the path metric held inthe search direction control circuit 5. Alternatively, the searchdirection control circuit or subtracts a branch metric in the backwarddirection which is calculated in the path decision circuit 4, from thepath metric held in the search direction control circuit 5. The searchdirection control circuit 5 then determines the above direction of thesearch by comparing the above path metric with a predeterminedthreshold, and makes the path decision circuit 4 carry out the searchoperation in the determined direction by supplying a search directioncontrol signal.

If the above path metric is larger than a threshold which ispredetermined in accordance with the Fano algorithm, it is determinedthat the forward search of the local most likely branch can becontinued. Or, if the above path metric is not larger than thethreshold, it is determined that the preceding forward search at thepreceding node, wherein the branch from the preceding node tothe abovenode was selected, was wrong, and the search operation must be restartedfrom the preceding node excluding the wrong branch.

According to the Fano algorithm, the path metric at each node is renewedwhen the operation is shifted from one node to the next, i. e., the pathmetric is not memorized at the timing of the operation at the next node.Therefore, when returning to the preceding node from the above wrongnode, the branch metric from the wrong node to the preceding node mustbe calculated and the calculated branch metric is subtracted from thepath metric at the wrong node to again obtain the path metric at thepreceding node. This is the backward search process in accordance withthe Fano algorithm.

The above operation by the path decision circuit 4 is a well-knownprocedure in accordance with the Fano algorithm. An example of the pathsearch according to the Fano algorithm is shown in FIG. 6, whereinreferences a, b, c, . . . each denote a node.

Going back to FIG. 4, the path memory 6 receives and holds the output ofthe path decision circuit 4 by the above forward search, and outputs thepreviously held decoded values back to the path decision circuit 4 foruse in the backward search

The address counter 7 outputs an address to both the buffer memory 1 andthe path memory 6. A newly received bit of coded data is written in anaddress which is determined by the above address from the address,counter 7, and one bit of decoded data which has been held in an addresswhich is also determined by the above address from the address counter 7in the path memory 6, is read out.

The pointer 2 outputs the operating address of the path decision circuit4, i. e., outputs the address of the node from which node a local mostlikely path (branch) is obtained by calculating branch metrics for allpossible branches from the node in the forward or backward direction.

Furthermore, in the prior art, some of the parity bits are removed fromthe series of output bits of the encoder at a predetermined rate beforebeing modulated on the sender side to increase the code rate, i. e., toincrease transmission efficiency. This method is called the puncturedmethod.

FIG. 7 shows an example of data generated by applying the puncturedmethod to the output of the encoder which generates a pair of dataincluding an information bit and a corresponding parity bit as shown inFIG. 5. In this example, parity bits except the 3n-th parity bits, P₃,P₆, . . . are removed from the series of FIG. 5. In addition, in FIG. 7,each (2n-1)-th bit and 2n-th bits are paired for QPSK modulation.

In the prior art, when the series of the punctured and paired signals(for example, having a form as in FIG. 7) are received through ademodulator at the receiver side, the form of the series of puncturedand paired signals as shown in FIG. 7 are transformed back to the formas shown in FIG. 5 by inserting dummy bits in the positions where theparity bits were previously removed. The transformed series of pairedsignals are then decoded in the sequential decoder as shown in FIG. 4.

Generally, fast operation of the sequential decoder is required.However, by the construction of FIG. 4, only one information bit isdecoded through one forward search operation. Further, by the abovepunctured method, the inserted dummy bits generally do not coincide withthe corresponding correct parity bits. Therefore, the above insertion ofdummy bits substantially increases the number of errors, and thus thebackward search operation of the Fano algorithm is more frequentlycarried out. This further lowers the decoding speed.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a sequential decoderwherein the speed of decoding systematic codes having a high code rateis increased.

According to the present invention, there is provided a sequentialdecoder for decoding a systematic and convolutional code signal having acode rate greater than 1/2 and carrying out error correction coding ofthe code signal. The sequential decoder comprises a path decision meansfor determining a local most likely path in a plurality of possiblepaths for a newly received information bit by calculating a branchmetric indicating the likelihood of each of the plurality of possible inaccordance with a predetermined algorithm. The path decision meanscomprises: a two-path comparing path decision means for receiving a pairof bits comprised of an information bit and a parity bit at one time anddetermining a local most likely path between two possible paths for theinformation bit; a four-path comparing path decision means for receivinga pair of information bits at one time and determining a local mostlikely path among four possible paths for the pair of information bits;a parity bit timing detecting means for detecting the timing of an inputof the pair of bits comprised of an information bit and a parity bit;and a selecting means for selecting an output of the two-path comparingpath decision means at the timing of the detection of the input of thepair of bits comprised of an information bit and a parity bit, andselecting an output of the four-path comparing path decision means atthe timing of the input of the pair of information bits.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a block digram of an encoder which receives a series of binarydata consisting of information bits and generates a parity bit for eachinformation bit;

FIG. 2 is a diagram of a coded result for an input data series"0011101";

FIG. 3 is a tree diagram;

FIG. 4 is a block digram of a conventional sequential decoder receivinga pair of signal bits consisting of an information bit and a parity bitat one time and sequentially decoding each signal bit using the Fanoalgorithm;

FIG. 5 is a diagram of coded signal bits pair consisting of aninformation bit and a parity bit;

FIG. 6 is a digram of the path search according to the Fano algorithm;

FIG. 7 is a diagram of data generated by applying the punctured methodto the coded signal bits as shown in FIG. 5;

FIG. 8 is a block diagram of the basic construction of the presentinvention;

FIG. 9 is a block diagram of typical operation of the present invention;

FIG. 10 is a block digram of the embodiment of the present invention;

FIG. 11 is a block diagram of the path decision circuit 4' in theconstruction of the sequential decoder according to the presentinvention;

FIG. 12 is a flowchart for the operation of the forward branch metriccalculating circuit 11 in FIG. 11; and

FIG. 13 is a block diagram of the forward branch metric calculatingcircuit 11 in FIG. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing the preferred embodiment of the present invention,first, the basic principle of the present invention is explained below.

FIG. 8 is a block diagram of the present invention.

In FIG. 8, reference numeral 61 denotes a two-path comparing pathdecision means, 62 denotes a four-path comparing path decision means, 63denotes a selecting means, 64 denotes a parity bit timing detectingmeans, and 65 denotes a path memory means. The function of each of theabove components and the relationship between each other are describedin the summary of the invention.

The sequential decoder according to the present invention receives apaired code signal having a code rate greater than 1/2 and having a formas shown in FIG. 7, i. e., a paired code consisting of a pair ofinformation bits and a periodically appearing pair of bits comprised ofan information bit and a parity bit, without inserting any dummy bits.When the above pair of bits comprised of an information bit and a paritybit is received, the sequential decoder carries out a two-path comparingpath decision in accordance with a predetermined algorithm. Or, when theabove pair of information bits are received, the sequential decodercarries out a four-path comparing path decision in accordance with thepredetermined algorithm.

The above "two-path comparing" means determines local most likely pathbetween two possible paths or branches (which correspond to the twopossible values "0" and "1" for one information bit) by comparing thelikelihoods for two paths in accordance with the predeterminedalgorithm. The above "four-path comparing" means determines a local mostlikely path among four possible paths or branches (which correspond tothe four possible combinations of the values of two information bits(1,1), (1,0), (0,0), and (0,1) by comparing the likelihoods for the fourpaths in accordance with the predetermined algorithm. An example of eachcase is shown in FIG. 9.

FIG. 10 is a block diagram of the construction of the embodiment of thepresent invention.

In FIG. 10, the same reference numerals as FIG. 4 are respectivelyassigned to the components which appear in both of FIGS. 4 and 10. Inaddition, in FIG. 10, the function of the path decision circuit 4' isdifferent from the aforementioned function of the path decision circuit4 in the construction of FIG. 4, and a parity detection circuit 3 isadded.

The input data of the construction of the sequential decoder shown inFIG. 10 is assumed to be a systematic and convolutional code signalhaving a code rate greater than 1/2, consisting of information bits andparity bits. The code signal is paired, and each pair of the series ofdata bits are simultaneously input into the sequential decoder at eachinput timing. Each pair consists of an information bit and a parity bit,or two information bits, for example, as shown in FIG. 7.

The latter input requirement does not impose a substantial limit on theapplicability of the sequential decoder of FIG. 10 and the presentinvention because any form of data consisting of information bits andparity bits and having a code rate greater than 1/2 can be transformedinto a two-row series form wherein each pair consists of an informationbit and a parity bit, or two information bits. Although the two-rowseries bits of coded signal shown in FIG. 7 is an example of the codedsignal which is generated by the punctured method, the scope of thepresent invention is not limited to the coded signal generated by thepunctured method. The present invention and therefore the embodimentshown in FIGS. 10 to 13 are generally applicable to all systematic andconvolutional code signals having a code rate greater than 1/2.

FIG. 11 is a block diagram of the construction of the path decisioncircuit 4' in the construction of the sequential decoder according tothe present invention.

In FIG. 11, reference numeral 11 denotes a forward branch metriccalculation circuit, 12 denotes a backward branch metric calculationcircuit, 13 denotes an internal encoder portion, 14 and 15 each denote ashift register, 16, 17, 18, 19, 20, and 21 each denote a flip-flopcircuit, 22 and 23 each denotes a selector, and 24, 25, 26, and 27 eachdenotes an adder of modulo two.

The forward branch metric calculation circuit 11 receives theaforementioned pair of coded signal bits at one time from the buffermemory 1, carries out the aforementioned forward search in the Fanoalgorithm. The forward branch metric calculation circuit 11 and outputsa branch metric from a node, the address of which is indicated by thepointer 2, to another node selected as a local most likely one by theabove forward search, and the decoded signals corresponding to theselected node. The forward branch metric calculation circuit 11 furtherreceives a search direction control signal, a skip signal, a parity bittiming detection signal, and the code rate data, as control signals.

The search direction control signal is the output of the aforementionedsearch direction control circuit 5 which is shown in FIG. 10 andfunctions the same as the search direction control circuit 5 shown inFIG. 4. The search direction control signal and indicates whether theforward search operation or the backward search should be carried out.

The code rate data is given to the forward branch metric calculationcircuit 11 and the backward branch metric calculation circuit 12 becausethe Fano metric depends on the code rate.

The skip signal is generated by an overflow monitor circuit and a skipcontrol circuit. The above overflow monitor circuit, the skip controlcircuit, and a switching portion are not shown in this application butare described in the U.S. Pat. No. 4,710,746 by the applicants. Theswitching portion (now shown) is incorporated in the final stage of theforward branch calculation circuit 11 to skip the error correctingoperation by the forward branch metric calculation circuit 11 when anoverflow of the buffer memory 1 due to an error-rich portion of thereceived data is detected in the overflow detector. Such an error-richportion is detected when the phase in the QPSK demodulator is notmatched. Therefore the above skip signal is applied to the forwardbranch metric calculation circuit 11 until the phase is matched.

The parity bit timing detection signal applied to the forward branchmetric calculation circuit 11 and the backward branch metric calculationcircuit 12 is generated in the parity bit timing detection circuit inFIG. 10.

The parity detection circuit 3 detects each timing of an input of a pairof bits comprised of an information bit and a parity bit in a two-bitform of a series of coded signals as shown in FIG. 7 according to theoutput of the pointer 2. When the input timing(s) of the pair of bitscomprised of an information bit and a parity bit in one code length isdetermined in advance, the parity detection circuit 3 can detect thetiming(s) of one or more inputs of one or more pairs of bits comprisedof an information bit and a parity bit, in each cycle of the codelength.

The operation of the forward branch metric calculation circuit 11 isshown in the flow chart FIG. 12.

In the step 71 of FIG. 12, the direction of the search operationaccording to the Fano algorithm is determined from the status of thereceived search direction control signal.

If it is determined that the direction of the search is forward, themaximum branch metric in the forward direction from the node whoseaddress is indicated by the pointer 2 is obtained, and the correspondingdecoded signal bits are output. At the same time, the maximum branchmetric is supplied to the search direction control circuit 5 of FIG. 10.

In the step 71 of FIG. 12, if it is determined that the direction of thesearch is backward, the operation goes to the step 73, and it isdetermined whether or not the operation has come back to the previousnode from a branch corresponding to a minimum branch metric.

If "yes" is determined in the step 73, i. e., when the operation hasjust come back from a branch corresponding to a minimum branch metric, aforward search completion signal is output from the forward branchmetric calculation circuit 11 in the step 74.

If "no" is determined in the step 73, i. e., when the operation has notcome back from a branch corresponding to a minimum branch metric, abranch from the node whose branch metric is the next smaller than thebranch metric of the branch through which the operation has just comeback from the above wrong branch node, is selected, and thecorresponding decoded signal bits are output. The above next smallerbranch metric is supplied to the search direction control circuit 5 inthe step 75.

Before explaining the operations of the other portions of theconstruction shown in FIG. 11, the construction of the forward branchmetric calculation circuit 11 is explained reference to FIG. 13.

FIG. 13 is a block diagram of the forward branch metric calculationcircuit 11 in FIG. 11.

In FIG. 13, reference numeral 31 denotes a two-path comparing pathdecision circuit, 32 denotes a four-path comparing path decisioncircuit, 33, 34, and 35 each denote a selector, 36 and 37 each denote anadder of modulo two, 38 and 39 each denote a Fano metric memory, and 40denotes an adder.

The two-path comparing path decision circuit 31 is constructed by ahardware logic circuit. The two-path comparing decision circuit 31realizes the aforementioned function of selecting a local most likelybranch between two possible branches from the operating nodecorresponding to a reception of a pair of coded signal bits consistingof an information bit and a parity bit.

The path decision circuit 32 is constructed by a hardware logic circuit.The four-path comparing path decision circuit 32 and realizes theaforementioned function of selecting a local most likely branch amongfour possible branches from the operating node corresponding to areception of a pair of coded signal bits consisting of two informationbits.

In each of the above constructions of the two-path comparing pathdecision circuit 31 and the four-path comparing path decision circuit32, the path metric can be defined in accordance with the proceduredisclosed in the aforementioned publications, R. M. Fano, in "HeuristicDiscussion of Probabilistic Decoding", IEEE Transaction of InformationTheory, Vol. IT-19, April 1963, pp.64-73, and U.S. Pat. No. 3,457,562.Further, the following publications disclose the Fano algorithm and theconstructions for carrying out the Fano algorithm: J. W. Layland and W.A. Lushbaugh, "Flexible High-Speed Sequential Decoder for Deep SpaceChannels", IEEE Transaction on Communication Technology, Vol. COM-19,No.5, October, 1971, pp.813-820; G. D. Forney, Jr., and E. K. Bower, "AHigh-Speed Sequential Decoder, Prototype Design and Test", IEEETransaction on Communication Technology, Vol. COM-19, No.5, October1971, pp.821-835; and K. Gilhousen and D. R. Lumb, "A Very High SpeedSequential Decoder" in the Proceedings of National TelecommunicationConference, 1972.

One of the above two-path comparing path decision circuit 31 and thefour-path comparing path decision circuit 32 operates in accordance withthe search direction control signal. The above-mentioned forward searchcompletion signal, and each of two bits of the decoded signals are eachselected in the corresponding selector 33, 34, or 35, in accordance withthe parity bit timing detection circuit 3.

To each of the two-path comparing path decision circuit 31 and thefour-path comparing path decision circuit 32, the previously decodeddata bits necessary for the decision in each circuit is provided throughthe aforementioned shift register 14 or 15.

The decoded data bits which are output through the selectors 34 and 35are each compared with the corresponding input bits at the adders 36 and37, and the outputs of the adders 36 and 37 are each applied to thecorresponding one of the Fano metric memories 38 and 39 as a read-outaddress. The Fano metric memories 38 and 39 hold the path metric valuescorresponding to all possible outputs of the corresponding adder 36 or37, and each of the Fano metric memories 38 and 39 outputs the forwardbranch metric value corresponding to the comparison result in the adders36 and 37. The outputs of the Fano metric memories 38 and 39 are addedin the adder 40, and then the output of the adder 40 is supplied to thesearch direction control circuit 5.

Going back to the construction of FIG. 11, the backward branch metriccalculation circuit 12 calculates the branch metric from the wrong node,which is detected in the search direction control circuit 6 by comparingthe path metric with a threshold determined in accordance with the Fanoalgorithm, back to the previous node at which the wrong branch leadingto the present wrong node was selected. The calculated result issupplied to the search direction control circuit 5 as a backward branchmetric. The backward branch metric is then added to the path metric heldin the search direction control circuit 5, and thus the path metric isrenewed corresponding to the above process of going back to a previousoperating node.

In the internal encoder portion 13 in FIG. 11, the shift register 14 andthe adders 24 and 25 form an internal encoder, and the shift register 15and the adders 26 and 27 form another internal encoder. Each of theinternal encoders is equivalent to the encoder which encodes thetransmitted signal on the sender side.

Each of the shift registers 14 and 15 shift data bits to the right orleft in accordance with the output address of the pointer 2 shown inFIG. 10. Each of a pair of newly decoded signal bits are input into thecorresponding one of the shift registers 14 and 15 from the left end.

Predetermined bits of the shift register 14 are connected to the adder24, and the adder 24 outputs a parity bit corresponding to decodedsignals from the forward branch metric calculation circuit 11. Theparity bit is used in the forward branch metric calculation circuit 11for determining the local most likely branch in accordance with the Fanoalgorithm.

The other adder 25 is connected to the bits of the shift register 14.Each of the bits is at a one-bit-delayed position from the correspondingone of the above predetermined bits for the adder 24. A parity bitobtained as the output of the adder 25 is used in the backward branchmetric calculation circuit 12 for calculating the backward branch metricin accordance with the Fano algorithm.

The above one bit delay is necessary because the operating node is atthe left end of a branch in a tree diagram when a forward branch metricis calculated, and the operating node is at the right end of a branch ina tree diagram when a backward branch metric is calculated. However, abranch metric is calculated as the path metric from the left end node ofthe branch to the right end node of the branch in the same manner inboth the forward branch metric calculation circuit 11 and the backwardbranch metric calculation circuit 12.

In the construction of FIG. 11, the flip-flop circuit 16 is providedbetween the forward branch metric calculation circuit 11 and the shiftregister 14 in the backward direction. The flip-flop circuit 17 isprovided between the backward branch metric calculation circuit 12 andthe shift register 15 in the backward direction. The flip-flop circuit18 is provided between the path memory 6 and the shift register 14 inthe forward direction, and the flip-flop circuit 20 is provided betweenthe path memory 6 and the shift register 15 in the forward direction. Inaddition, the flip-flop circuit 19 and the selector 22 are connected inseries between the path memory 6 and the shift register 14 in thebackward direction, and the flip-flop circuit 21 and the selector 23 areconnected in series between the path memory 6 and the shift register 15in the backward direction. The selector 22 receives the outputs of theflip-flop circuits 18 and 19 and the output of the path memory 6, andapplies its output to the flip-flop circuit 19. The selector 23 receivesthe outputs of the flip-flop circuits 20 and 21 and the output of thepath memory 6, and applies its output to the flip-flop circuit 20.

When a branch is selected and the branch metric is calculated in thestep 75 of FIG. 12, previously decoded data which is held in theconstruction between the forward branch metric calculation circuit 11and the path memory 6 are used. The decoded data to be used in theforward branch metric calculation circuit 11 is transferred through theselectors 22 and 23, the flip-flop circuits 19 and 21, the shiftregisters 14 and 15, and the flip-flop circuits 16 and 17 to the forwardbranch metric calculation circuit 11. Or when a backward branch metricis calculated, the decoded data to be used in the backward branch metriccalculation circuit 12 is transferred through the selectors 22 and 23,the flip-flop circuits 19 and 21, and the shift registers 14 and 15.

When a branch is selected and the branch metric is calculated in thestep 75 of FIG. 12, decoded data bits (information bits) which aregenerated in the preceding operating node in the backward direction areheld in the flip-flop circuits 16 and 17.

A decoded data bit output from the right end of the shift register 14 or15 is held respectively in the flip-flop circuit 18 or 20. If data bitsbetween the forward branch metric calculation circuit 11 and the pathmemory 6 are shifted in the backward direction in the next operation,the data bit held in the flip-flop circuit 18 or 20 is input into theflip-flop circuit 19 or 21 through the selector 22 or 23, and then inputinto the right end bit of the shift register 14 or 15. Since it takesconsiderable time to read out a data bit held in the path memory, theabove construction of the flip-flop circuits 18, 19, 20, and 21, and theselectors 22 and 23 eliminate the waiting time for reading out a firstbit from the path memory 6.

Further, since the pointer address is not shifted when the thresholdvalue is lowered in accordance with the Fano algorithm, the decoded databits in the flip-flop circuits 19 and 21 are each maintained in a loopwhich is made by connecting the output of the flip-flop circuit 19 or 21to its own input, respectively.

In the conventional sequential decoder, only a two-path decision circuitand only one shift register, through which decoded information bits areshifted to the right or left, and in which internal encoding (generationof parity bits) is carried out using bits at predetermined positions,are provided in the path decision circuit 4 in the construction of FIG.4. Therefore, only one information bit is processed for one outputaddress of the pointer 5 of FIG. 4. Since there is a limit in therenewal speed of the pointer 5, which is determined by the operatingclock of the sequential decoder, the renewal speed imposes a limit onthe processing speed of the decoding.

However, in the construction of the embodiment of the present inventionas shown in FIGS. 11 and 13, when a pair of information bits is inputinto the sequential decoder, the decoded output of the four-pathcomparing path decision circuit 32 including two decoded informationbits are selected as the output of the forward branch metric calculationcircuit 11. Then each of the decoded information bits is input into theleft end bit of the corresponding one of the shift registers 14 and 15.Therefore, when a pair of information bits are input into the sequentialdecoder, two information bits are processed for an address of thepointer 2. Thus, the processing speed of the sequential decoder isincreased by the present invention.

We claim:
 1. A sequential decoder for decoding a systematic andconvolutional code signal having a code rate greater than 1/2 andcarrying out error correction coding of said code signal,comprising:path decision means for determining a local most likely pathin a plurality of possible paths for a newly received information bit bycalculating a branch metric indicating likelihood of each of saidplurality of possible paths in accordance with a predeterminedalgorithm, said path decision means comprising:two-path comparing pathdecision means for receiving a pair of bits comprised of an informationbit and a parity bit at one time and determining a local most likelypath between two possible paths for said information bit; four-pathcomparing path decision means for receiving a pair of information bitsat one time and determining a local most likely path among four possiblepaths for said pair of information bits; parity bit timing detectingmeans for detecting a timing of an input of said pair of bits comprisedof an information bit and a parity bit; and selecting means forselecting an output of said two-path comparing path decision means whensaid input timing of said pair of bits comprised of an information bitand a parity bit is detected, and selecting an output of said four-pathcomparing path decision means when said pair of information bits isreceived.
 2. A sequential decoder according to claim 1, furthercomprising a path memory for receiving and holding an output of saidpath decision circuit; andwherein each of said two-path comparing pathdecision means and said four-path comparing path decision meansrespectively comprise a shift register means for transferring eachoutput bit of said path decision means by shifting between said pathdecision means and said path memory.
 3. A sequential decoder accordingto claim 2, wherein, each of said two-path comparing path decision meansand said four-path comparing path decision means respectively furthercomprise an internal encoder along with each of said shift registers. 4.A sequential decoder according to claim 1, further comprising a pointerfor outputting an operating address of said path decision circuit,corresponding to each pair of bits input into said path decisioncircuit, and whereinsaid parity bit timing detecting means detectingsaid input timing of said pair of bits comprised of an information bitand a parity bit by monitoring each output of said pointer.
 5. A methodfor decoding a systematic and convolutional code signal having a coderate greater than 1/2 and carrying out error correction coding of thecode signal, said method comprising the steps of:(a) determining thedirection of the search operation; (b) obtaining a maximum branch metricin the forward direction when the direction of the search is determinedto be forward; (c) obtaining a branch corresponding to a minimum branchmetric when the direction of the search is determined to be backward;(d) outputting a search completion signal when the operation hasreturned from a branch corresponding to a maximum branch metric; and (e)outputting decoded signal bits when the operation has returned from abranch corresponding to a minimum branch metric.